Multilevel metal interconnect structures are routinely employed to provide electrical wiring for a high density circuitry, such as semiconductor devices on a substrate. Continuous scaling of semiconductor devices leads to a higher wiring density as well as an increase in the number of wiring levels. For example, a 3D NAND stacked memory device may include a high density of bit lines electrically connected to respective drain regions through underlying contact via structures. Misalignment between the contact via structures and the bit lines can cause undesirable electrical shorts or electrical opens.